The continuous pressure to reduce size, weight, and cost of semiconductor devices, while at the same time increasing the functionality thereof, has led to innovative, cost-effective 3D packaging concepts. Among 3D packaging techniques, through-silicon-via (TSV) electrodes are able to provide the shortest and most beneficial vertical connections. To realize TSV, essentially vertical connections are etched through the silicon wafer and filled with conductive material. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.
Connection lengths can be as short as the thickness of a chip and hence high density, high aspect ratio connections are possible. TSV interconnections also help to reduce the RC delays and power consumption by physically reducing the length of interconnects between the functional units/blocks on a chip. The technologies engaged with TSV chip connection include TSV etching, insulator/barrier/seed deposition, via filling, surface copper removal, wafer thinning, bonding/stacking, inspection, test, etc.
One of the issues to be solved in damascene-like TSV integration processes is the selective removal of overburden of conductive material (e.g. Cu) and barrier material (e.g. a Ta or Ti comprising layer) after completing the filling of the TSV, by applying Chemical Mechanical Polishing techniques (CMP). The control over the CMP process is extremely important: all the conductive material and barrier material has to be removed from the surface in order to prevent shortcuts in the final device. On the other hand, not too much surface (e.g. SiO2) material should be consumed in the removal step in order to prevent a too strong attack of the underlying structures (e.g. contact plugs) that will allow the TSV to be connected to the conventional interconnects. Due to the small difference in material selectivity of the CMP process for the barrier material (e.g. TaN or TiN) versus the surface material (e.g. SiO2) the CMP removal process has an extremely narrow process window. A very thick barrier layer has to be deposited in order to ensure a continuous coverage of the barrier layer all over the surface and the polishing slurries are not selective enough towards the underlying (oxide) surface layer. A slight over-polish, which is a standard procedure to deal with non-uniformities with CMP, will strongly affect the surface underneath. A loss of several tenths of percent of the total thickness can be expected. This would result in distorted electrical performance or completely destroyed device operation.
The problem to be solved is thus to remove the overburden of barrier and conductive material after filling of a Through Silicon Via (TSV) using chemical mechanical polishing (CMP) thereby creating a larger process window to compensate for non-uniformity in deposition and polishing such that a 10-20% “over” polish can be allowed without thereby damaging the dielectric stack (in other words without affecting other integration steps).
The process control of the CMP step to remove the overburden of barrier, seed and conductive material after filling of a Through Silicon Via (TSV) is extremely important since all the barrier, seed and conductive material has to be removed from the surface in order to prevent shortcuts in the final device. On the other hand not too much dielectric underneath (oxide) should be consumed in order to prevent a too strong attack of the vias (being contact plugs or vias at any metal layer below) that will allow the TSV to be connected to the conventional interconnects.
As stated, the process window for the CMP step is extremely narrow because a rather thick overburden of barrier material has to be deposited in order to ensure an continuous barrier deposition all over the Via surface (sidewalls) and the slurries are often not selective enough towards the underlying dielectric layer (oxide). The thickness of the barrier layer on the surface is a consequence of (a result of) the poor conformality of state of the art Plasma Vapor Deposition (PVD) layers which may be not higher than 10% because of the low deposition efficiency onto the sidewalls of high aspect ratio vias (typically very low efficiency is achieved at the lower part of the sidewalls) A slight over-polish, which is a standard procedure to deal with non-uniformities with CMP, will strongly affect the PMD (Pre Metal Deposited) or IMD (Inter metal deposited) dielectric layer (oxides).
Through Silicon Vias may be integrated during Front End Of Line processing. In this case the TSV is etched through the Pre-Metal Dielectric (PMD) stack deposited on a semiconductor wafer (in most cases a silicon wafer), said wafer comprising active components (i.e. transistors etc) of an Integrated Circuit (IC), and through the silicon wafer itself, in order to contact an underlying IC. A TSV may also be integrated at a later stage of the processing during Back End Of Line processing, where several levels of Inter Metal Dielectric stacks (IMD) are deposited on a silicon wafer, each level comprising contact vias and trenches filled with metal for forming interconnects. The TSV is then etched through the several IMD levels and through the underlying silicon substrate, again in order to contact an underlying IC.
A solution to the problem of the insufficient window for CMP which might have been proposed on the basis of general knowledge of CMP would be to introduce the CMP stopping layer prior to the start of TSV processing (typically just before patterning the TSV). Nevertheless, the introduction of the CMP stopping layer in this module results in a number of additional integration problems in the following IMD module. Indeed this additional stopping layer needs to be etched in order to contact vias (to contact device or metal-1) while at the same time the Cu of the TSV is fully exposed. This is typically done in a dry etch step. The exposed Cu is contaminating the etch chamber, which results in a drift of the etch-process as a function of the etch-time and number of etched wafers. Another unwanted effect is the corrosion of the Cu surface of the TSV during exposure in the etch chamber, which results in a higher (unwanted) resistivity. FIG. 1 illustrates the above described problem in a final device having at least one Through Substrate Via (TSV) 4 fabricated according to the method suggested above, wherein a PMD stack is provided on top of a substrate 1. A contact via 3 is produced and filled, prior to the production of a TSV 4. A CMP stop layer 5′ is deposited prior to the etching of the TSV. The problem indicated is the fact that the CMP stopping layer 5′ still needs to be opened (above the contact via 3) while Cu is exposed in Through Substrate Vias (TSV).
FIG. 2 illustrates a typical problem in a final device having at least one Through Silicon Vias (TSV) fabricated according to the state of the art method. Resist footing occurs (see arrow) in the resist 30 after patterning of the opening to determine the contact via 3. Presently this problem is solved by applying a thin oxide layer on the PMD stack.